1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated field effect transistors, such as MOS transistor structures, connected to a contact structure including a plurality of contact plugs.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. Presently, and in the foreseeable future, the majority of integrated circuits are, and will be, based on silicon devices, due to the high availability of silicon substrates and due to the well-established process technology that has been developed over the past decades. A key issue in developing integrated circuits of increased packing density and enhanced performance has been the scaling of transistor elements, such as MOS transistor elements, to provide the great number of transistor elements that may be necessary for producing modern CPUs and memory devices. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length has been considered necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length.
For example, for a reduced gate length, typically the respective thickness of the gate insulation layer is also to be reduced in order to maintain the controllability of the conductive channel. Since the thickness of gate insulation layers comprising silicon dioxide are currently approaching the practical limits with respect to breakthrough voltage and leakage currents, while other strategies, such as dielectric materials of increased permittivity and the like, may suffer from reduced reliability, it has been proposed to enhance the drive current capability of advanced field effect transistors for a given design dimension by creating a respective strain in the channel region in order to appropriately modify the charge carrier mobility therein. For example, creating a substantially uniaxial compressive or tensile strain in the channel region may result in an increased mobility of holes and electrons, respectively. One efficient mechanism for generating a respective strain in the channel regions of field effect transistors includes the provision of a highly stressed dielectric material that covers the transistor, wherein the intrinsic stress may be transferred into the underlying semiconductor material so as to finally obtain a respective strain in the channel region. For example, well-approved materials, such as silicon dioxide, silicon nitride, carbon enriched silicon nitride and the like, may be formed by plasma enhanced chemical vapor deposition (PECVD) techniques, wherein respective process parameters may be efficiently controlled in order to obtain a desired degree and type of intrinsic stress. For instance, silicon nitride may be deposited with a high intrinsic compressive stress of up to 3 GPa or even higher, which may therefore be advantageously used in order to enhance the performance of P-type transistors. Similarly, silicon nitride may also be deposited with a moderately high tensile stress in the range of 1 GPa and higher, thereby providing the potential for increasing the drive current capability of N-channel transistors. These highly stressed materials may be incorporated into the interlayer dielectric material that covers and passivates the transistor elements, wherein respective wiring levels, so-called metallization layers, may be formed on and above the interlayer dielectric material. Consequently, in combination with reduced transistor dimensions, the respective strain-inducing mechanisms may allow the fabrication of high performance transistor elements. However, the finally obtained performance of integrated circuits and of individual transistor elements may not only depend on the specific transistor characteristics but may also be determined by the respective wiring regime that provides mutual electrical connection of individual circuit elements according to the specified circuit layout. Due to the increasing number of circuit elements per unit area, typically an even increased number of connections between these circuit elements may have to be provided, which may required sophisticated interconnect structures, wherein the continuous reduction of the cross-sectional areas demands highly conductive material and reduced parasitic capacitance between neighboring conductors. Consequently, in the respective metallization levels, highly conductive materials, such as copper in combination with low-k dielectric materials, may be used.
Of great importance for the overall performance of individual transistor elements, however, is also a respective contact structure which provides the electrical connection between the drain and source regions and the metallization level. Thus, the respective contact plugs or contact elements may have to provide a low contact resistance while at the same time not unduly affect other transistor characteristics, such as switching speed and the like. It turns out, however, that it is difficult in conventional strategies to concurrently meet these two requirements, as will be explained with reference to FIGS. 1a and 1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, for instance, a silicon-based substrate or any other appropriate carrier material having formed thereabove a silicon-based semiconductor layer 102. Furthermore, a field effect transistor 110 is formed in and above the semiconductor layer 102. The transistor 110 may comprise a gate electrode 114 formed on a gate insulation layer 115 that separates the gate electrode 114 from a channel region 116 positioned in the semiconductor layer 102. Moreover, a respective spacer structure 113 may be provided on sidewalls of the gate electrode 114. The transistor 110 further comprises highly doped semiconductor regions 111, 112 acting as a drain and a source, respectively. Hence, the region 111 may represent a source region while the region 112 may represent a drain region. It should be appreciated that the configurations of the source and drain regions 111, 112 may be substantially identical in many well-established transistor architectures, wherein the different function of the source region 111 with respect to the drain region 112 may be defined by the circuit layout, that is, the source region 111 may typically be connected to different voltage nodes compared to the drain region 112 for a specified type of transistor. For example, for an N-channel transistor, the source region 111 may actually act as a source of electrons, wherein a respective conductive channel may build up in the channel region 116 on application of an appropriate control voltage to the gate electrode 114 from the source side to the drain side, wherein the respective electrons may have a maximum kinetic energy at the drain side after acceleration by the voltage difference between the source region 111 and the drain region 112 at the beginning of a corresponding switching operation. Moreover, metal silicide regions 117 may be formed in the drain and source regions 112, 111 and on the gate electrode 114 to reduce the signal propagation delay in the gate electrode 114 and to reduce the contact resistance in the drain and source regions 112, 111.
The semiconductor device 100 further comprises an interlayer dielectric material 120, which encloses and passivates the transistor 110 and which may be comprised of two or more materials. Frequently, a silicon dioxide based material may be provided in the form of a layer 122 providing the desired passivating characteristics. Moreover, an etch stop layer 121 is typically located above the transistor 110, which exhibits a high etch selectivity with respect to the material of the layer 122 so as to allow an efficient control of a respective etch process for patterning the layer 122 in order to form respective contact plugs 131, 132 connecting to the source region 111 and the drain region 112, respectively. For instance, the etch stop layer 121 may be comprised of silicon nitride which may have a high etch resistivity with respect to a plurality of anisotropic etch recipes for etching silicon dioxide based materials. The contacts or contact plugs 131, 132 may be formed on the basis of any appropriate conductive material wherein, as previously explained, metals may typically be used to provide low contact resistance so as to not unduly negatively affect the overall performance of the transistor 110. For example, tungsten, copper, aluminum, or any other metals may typically be used wherein appropriate conductive barrier layers (not shown) may be provided in combination with the respective conductive material.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of the following processes. The semiconductor layer 102 may be patterned on the basis of well-established process techniques in order to define appropriate active areas for forming therein one or more transistor elements, such as the transistor 110, or other circuit elements. For this purpose, shallow trench isolation structures may be formed by lithography, etch, deposition and planarization techniques. Thereafter, a basic doping concentration may be created within the respective active regions in accordance with the respective transistor characteristics. Thereafter, the gate electrode 114 and the gate insulation layer 115 may be formed on the basis of well-established strategies including the deposition and/or oxidation or other modification of a base material to obtain the gate insulation layer 115 with a desired thickness, which may be approximately 1-2 nm for silicon dioxide based layers of highly advanced field effect transistors. The gate electrodes 114 may be formed by deposition and subsequent sophisticated patterning techniques. Thereafter, the drain and source regions 112, 111 may be formed on the basis of appropriately designed implantation cycles using the spacer structure 113, which may have different lateral dimensions during the respective implantation processes. Intermittently, and after the implantation processes, appropriate anneal processes may be performed to activate the dopants and re-crystallize the drain and source regions 112, 111. If required, the metal silicide regions 117 may then be formed in the gate electrode 114 and the drain and source regions 112, 111. Next, the etch stop layer 121 may be formed, wherein typically, in advanced applications, a high internal stress may be generated in the layer 121 in order to provide the required type and amount of strain in the channel region 116, thereby enhancing the charge carrier mobility therein and thus the drive current capability. As previously explained, silicon nitride and other materials may be advantageously deposited so as to exhibit a high intrinsic stress. Thereafter, the dielectric layer 122 may be formed by any appropriate deposition technique, possibly followed by a planarization step in order to provide superior surface characteristics for a subsequent lithography and patterning sequence in order to form respective openings in the interlayer dielectric material 120. Thereafter, the respective openings may be filled with an appropriate material, such as tungsten, wherein an appropriate barrier material may be provided, as previously explained.
During the operation of the transistor 110, the performance thereof is determined by the characteristics of the conductive path defined by the contact 131 through the silicide region 117 into the source region 111, the channel region 116 into the drain region 112 and via the metal silicide region 117 and the contact element 132 back into a corresponding metal line in a metallization layer formed above the interlayer dielectric material 120. For instance, by creating a respective strain in the channel region 116 and enhancing the dopant profiles in the drain and source regions 112, 111, superior switching characteristics and current drive capability may be achieved. To maintain a desired low contact resistance, typically a plurality of respective contact elements 131 connecting to the source region 111 and a plurality of contact elements 132 connecting to the drain region 112 are provided. On the other hand, the contact elements 131, 132 may have a significant influence on the overall stress transfer into the channel region 116, since the highly stressed material of the etch stop layer 121 may be removed in these areas, which therefore may not contribute to the desired enhancement of the drive current capability. Furthermore, the fringing capacitance with respect to the gate electrode 114, caused by the contacts 131 and 132, may also have an adverse affect on the overall transistor performance. Thus, from the point of view of a reduced contact resistance, a large number of respective contact elements 131, 132 with moderately large lateral target dimensions may be desirable, while in view of strain characteristics and in view of the fringing capacitance with respect to the gate electrode 114, a reduced number and/or size of the contact elements 131, 132 is desirable. Consequently, the design of the contact elements 131, 132 is a compromise between these requirements.
FIG. 1b schematically illustrates a top view of the semiconductor device 100, wherein the respective contact elements 131 at the source side and the respective contact elements 132 at the drain side are provided with a specific layout defined by the lateral dimension, indicated as L, of the contact elements and also by a respective distance, indicated as D, wherein these dimensions L, D are to be understood as design dimensions, i.e., as target values, which may slightly vary according to process fluctuations in actual devices. The respective lateral dimension L and the lateral distance D are typically the same for all of the circuit elements in the semiconductor device 100. Consequently, a respective gain in transistor performance obtained by device scaling and advanced strain-inducing mechanisms may significantly depend on the contact structure and may result in a performance gain less than expected due to the above-explained adverse influence on specific transistor characteristics.
The present disclosure is directed to various techniques and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.